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 Features
* Low-voltage and Standard-voltage Operation * * * * * * * * * * * *
- 1.8v (VCC = 1.8V to 3.6V) - 2.5v (VCC = 2.5V to 3.6V) Internally Organized 65,536 x 8 Two-wire Serial Interface Schmitt Triggers, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 1 MHz (3.6V), 400 kHz (1.8V, 2.5V) Compatibility Write Protect Pin for Hardware and Software Data Protection 128-byte Page Write Mode (Partial Page Writes Allowed) Self-timed Write Cycle (5 ms Max) High Reliability - Endurance: 1,000,000 Write Cycles - Data Retention: 40 Years Lead-free/Halogen-free Devices 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-ball dBGA2, and 8-lead Ultra Thin Small Array (SAP) Packages Die Sales: Wafer Form, Waffle Pack and Bumped Die
Two-wire Serial EEPROM
512K (65,536 x 8)
AT24C512B
with Three Device Address Inputs
Description
The AT24C512B provides 524,288 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device's cascadable feature allows up to eight devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-pin PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-ball dBGA2 and 8-lead Ultra Thin SAP packages. In addition, the entire family is available in a 1.8V (1.8V to 3.6V) version.
Preliminary
Table 1. Pin Configurations
Pin Name A0-A2 SDA SCL WP Function Address Inputs Serial Data Serial Clock Input Write Protect
A0 A1 A2 GND
8-lead TSSOP
1 2 3 4 8 7 6 5 VCC WP SCL SDA
A0 A1 A2 GND
8-lead PDIP
1 2 3 4 8 7 6 5 VCC WP SCL SDA
8-lead SOIC
A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA
8-ball dBGA2 8-lead Ultra Thin SAP
VCC WP SCL SDA 8 7 6 5 1 2 3 4 A0 A1 A2 GND
VCC WP SCL SDA 8 7 6 5 1 2 3 4 A0 A1 A2 GND
Bottom View
Bottom View
Rev. 5112D-SEEPR-3/07
1
Absolute Maximum Ratings*
Operating Temperature..................................-55C to +125C Storage Temperature .....................................-65C to +150C Voltage on Any Pin with Respect to Ground .................................... -1.0V to +7.0V Maximum Operating Voltage ............................................ 4.3V DC Output Current........................................................ 3.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 1. Block Diagram
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AT24C512B [Preliminary]
5112D-SEEPR-3/07
AT24C512B [Preliminary]
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other AT24Cxx devices. When the pins are hardwired, as many as eight 512K devices may be addressed on a single bus system. (Device addressing is discussed in detail under "Device Addressing," page 8.) A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel(R) recommends always connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10k or less. WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected directly to Vcc, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10k or less.
Memory Organization
AT24C512B, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of 128-bytes each. Random word addressing requires a 16-bit data word address.
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5112D-SEEPR-3/07
Table 2. Pin Capacitance(1) Applicable over recommended operating range from: TA = 25C, f = 1.0 MHz, VCC = +1.8V to +3.6V
Symbol CI/O CIN Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance (A0, A1, SCL) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V
Table 3. DC Characteristics Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +1.8V to +3.6V (unless otherwise noted)
Symbol VCC1 ICC1 ICC2 ISB1 ISB2 ILI ILO VIL VIH VOL2 VOL1 Note: Parameter Supply Voltage Supply Current Supply Current Standby Current (1.8V option) Standby Current (2.5V option) Input Leakage Current Output Leakage Current Input Low Level(1) Input High Level(1) Output Low Level Output Low Level VCC = 3.0V VCC = 1.8V IOL = 2.1 mA IOL = 0.15 mA VCC = 3.6V VCC = 3.6V VCC = 1.8V VCC = 3.6V VCC = 2.5V VCC = 3.6V VIN = VCC or VSS VOUT = VCC or VSS -0.6 VCC x 0.7 READ at 400 kHz WRITE at 400 kHz VIN = VCC or VSS VIN = VCC or VSS 0.10 0.05 Test Condition Min 1.8 1.0 2.0 Typ Max 3.6 2.0 3.0 1.0 3.0 2.0 3.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4 0.2 Units V mA mA A A A A A A V V V V
1. VIL min and VIH max are reference only and are not tested.
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AT24C512B [Preliminary]
5112D-SEEPR-3/07
AT24C512B [Preliminary]
Table 4. AC Characteristics (Industrial Temperature) Applicable over recommended operating range from TAI = -40C to +85C, VCC = +1.8V to +3.6V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2.
1.8-volt, 2.5-volt Symbol fSCL tLOW tHIGH ti tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Endurance(1) Notes: Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Noise Suppression Time
(1)
3.6-volt Min Max 1000 0.4 0.4 Units kHz s s 50 0.05 0.5 0.25 0.25 0 100 0.55 ns s s s s s ns 0.3 100 0.25 50 s ns s ns 5 ms Write Cycles
Min
Max 400
1.3 0.6 100 0.05 1.3 0.6 0.6 0 100 0.3 300 0.6 50 5 0.9
Clock Low to Data Out Valid Time the bus must be free before a new transmission can start(1) Start Hold Time Start Set-up Time Data In Hold Time Data In Set-up Time Inputs Rise Time Inputs Fall Time
(1)
(1)
Stop Set-up Time Data Out Hold Time Write Cycle Time 25C, Page Mode, 3.3V
1,000,000
1. This parameter is ensured by characterization. 2. AC measurement conditions: RL (connects to VCC): 1.3 k (2.5V, 3.6V), 10 k (1.8V) Input pulse voltages: 0.3 VCC to 0.7 VCC Input rise and fall times: 50 ns Input and output timing reference voltages: 0.5 VCC
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5 on page 7). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5 on page 7). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.
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5112D-SEEPR-3/07
STANDBY MODE: The AT24C512B features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations. Software Reset: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps: (a) Create a start bit condition, (b) clock 9 cycles, (c) create another start bit followed by stop bit condition as shown below. The device is ready for next communication after above steps have been completed. Figure 1. Protocol Reset Condition
Start bit Dummy Clock Cycles Start bit Stop bit
SCL
1
2
3
8
9
SDA
Figure 2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)
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AT24C512B [Preliminary]
5112D-SEEPR-3/07
AT24C512B [Preliminary]
Figure 3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
SCL
SDA
8th BIT WORDn
ACK
twr STOP CONDITION
(1)
START CONDITION
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
Figure 4. Data Validity
Figure 5. Start and Stop Definition
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5112D-SEEPR-3/07
Figure 6. Output Acknowledge
Device Addressing
The 512K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 7 on page 9). The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all two-wire EEPROM devices. The 512K uses the three device address bits A2, A1, A0 to allow as many as eight devices on the same bus. These bits must compare to their corresponding hardwired input pins. The A2, A1 and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the device will return to a standby state. DATA SECURITY: The AT24C512B has a hardware data protection scheme that allows the user to Write Protect the whole memory when the WP pin is at VCC.
Write Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0". The addressing device, such as a microcontroller, then must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on page 10). PAGE WRITE: The 512K EEPROM is capable of 128-byte page writes. A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 127 more data words. The EEPROM will respond with a "0" after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 9 on page 10).
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AT24C512B [Preliminary]
5112D-SEEPR-3/07
AT24C512B [Preliminary]
The data word address lower 7 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 128 data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten. The address roll over during write is from the last byte of the current page to the first byte of the same page. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The Read/Write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a "0", allowing the read or write sequence to continue.
Read Operations
Read operations are initiated the same way as write operations with the exception that the Read/Write select bit in the device address word is set to "1". There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by "1". This address stays valid between operations as long as the chip power is maintained. The address roll over during read is from the last byte of the last memory page, to the first byte of the first page. Once the device address with the Read/Write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does generate a following stop condition (see Figure 10 on page 10). RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the Read/Write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 11 on page 10). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will roll over and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 12 on page 11). Figure 7. Device Address
1 MSB
0
1
0
A2
A1
A0
R/W LSB
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5112D-SEEPR-3/07
Figure 8. Byte Write
Figure 9. Page Write
Figure 10. Current Address Read
Figure 11. Random Read
10
AT24C512B [Preliminary]
5112D-SEEPR-3/07
AT24C512B [Preliminary]
Figure 12. Sequential Read
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5112D-SEEPR-3/07
Ordering Information
Ordering Code AT24C512B-PU (Bulk form only) AT24C512B-PU25 (Bulk form only) AT24C512BN-SH-B(1) (NiPdAu Lead Finish) AT24C512BN-SH-T(2) (NiPdAu Lead Finish) AT24C512BN-SH25-B AT24C512BN-SH25-T AT24C512BW-SH-T
(2) (1)
Voltage 1.8 2.5 1.8 1.8 2.5 2.5 1.8 1.8 2.5 2.5 1.8 1.8 2.5 2.5 1.8 2.5 1.8 1.8
Package 8P3 8P3 8S1 8S1 8S1 8S1 8S2 8S2 8S2 8S2 8A2 8A2 8A2 8A2 8Y7 8Y7 8U4-1 Die Sale
Operation Range
(NiPdAu Lead Finish) (NiPdAu Lead Finish)
(2)
AT24C512BW-SH-B(1) (NiPdAu Lead Finish) (NiPdAu Lead Finish)
(1)
AT24C512BW-SH25-B
(NiPdAu Lead Finish)
AT24C512BW-SH25-T(2) (NiPdAu Lead Finish) AT24C512B-TH-B(1) (NiPdAu Lead Finish) AT24C512B-TH-T
(2)
Lead-free/Halogen-free/ Industrial Temperature (-40C to 85C)
(NiPdAu Lead Finish)
(1)
AT24C512B-TH25-B AT24C512B-TH25-T
(NiPdAu Lead Finish) (NiPdAu Lead Finish)
(2)
(2)
AT24C512BY7-YH-T(2) (NiPdAu Lead Finish) AT24C512BY7-YH25-T AT24C512BU4-UU-T AT24C512B-W-11 Notes:
(3) (2)
(NiPdAu Lead Finish)
(NiPdAu Lead Finish)
Industrial Temperature (-40C to 85C)
1. "-B" denotes bulk 2. "-T" denotes tape and reel. SOIC = 4K per reel. TSSOP and dBGA2 = 5K per reel. SAP = 3K per reel. EIAJ = 2K per reel. 3. Available in waffle pack, tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing.
Package Type 8P3 8S1 8S2 8A2 8Y7 8U4-1 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8-lead, 0.200" Wide Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8-lead, 6.00 mm x 4.90 mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP) 8-ball, die Ball Grid Array Package (dBGA2) Options -1.8 -2.5 Low-voltage (1.8V to 3.6V) Low-voltage (2.5V to 3.6V)
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AT24C512B [Preliminary]
5112D-SEEPR-3/07
AT24C512B [Preliminary]
Packaging Information 8P3 - PDIP
E E1
1
N
Top View
c eA
End View
D e D1 A2 A
SYMBOL
COMMON DIMENSIONS (Unit of Measure = inches) MIN - NOM - MAX NOTE
A A2 b b2 b3 c D
0.210 0.195 0.022 0.070 0.045 0.014 0.400
-
2
0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240
0.130 0.018 0.060 0.039 0.010 0.365
-
5 6 6
3 3 4 3
b2 b3
4 PLCS
L
D1 E E1 e eA L
b
0.310 0.250 0.100 BSC 0.300 BSC
0.325 0.280
Side View
4 0.150 2
0.115
0.130
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B
R
13
5112D-SEEPR-3/07
8S1 - JEDEC SOIC
C
1
E
E1
N
L
Top View End View
e B A
SYMBOL COMMON DIMENSIONS (Unit of Measure = mm) MIN 1.35 0.10 0.31 0.17 4.80 3.81 5.79 NOM - - - - - - - 1.27 BSC 0.40 0 - - 1.27 8 MAX 1.75 0.25 0.51 0.25 5.00 3.99 6.20 NOTE
A1
A A1 B C
D
D E1 E
Side View
e L
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. B
R
14
AT24C512B [Preliminary]
5112D-SEEPR-3/07
AT24C512B [Preliminary]
8S2 - EIAJ SOIC
C
1
E
E1
L
N
TOP VIEW
e A
SYMBOL
END VIEW
b
COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE
A1
A A1 b C
1.70 0.05 0.35 0.15 5.13 5.18 7.70 0.51 0 1.27 BSC
2.16 0.25 0.48 0.35 5.35 5.40 8.26 0.85 8 4 2, 3 5 5
D
D E1 E
SIDE VIEW
Notes: 1. 2. 3. 4. 5.
L e
This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. Determines the true geometric position. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
4/7/06 TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) DRAWING NO. REV. D
R
2325 Orchard Parkway San Jose, CA 95131
8S2
15
5112D-SEEPR-3/07
8A2 - TSSOP
3 21
Pin 1 indicator this corner
E1
E
L1
N L
Top View
End View
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 2.90 NOM 3.00 6.40 BSC 4.30 - 0.80 0.19 4.40 - 1.00 - 0.65 BSC 0.45 0.60 1.00 REF 0.75 4.50 1.20 1.05 0.30 4 3, 5 MAX 3.10 NOTE 2, 5
b
A
D E E1 A
e D
A2
A2 b e
Side View
L L1
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02
R
2325 Orchard Parkway San Jose, CA 95131
TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
DRAWING NO. 8A2
REV. B
16
AT24C512B [Preliminary]
5112D-SEEPR-3/07
AT24C512B [Preliminary]
8Y7 - UTSAP
PIN 1 INDEX AREA
A
PIN 1 ID
D E1
D1
L
E A
A1
b
e e1
COMMON DIMENSIONS (Unit of Measure = mm)
SYMBOL
MIN - 0.00 5.80 4.70 3.30 3.90 0.35
NOM - - 6.00 4.90 3.40 4.00 0.40 1.27 TYP 3.81 REF
MAX 0.60 0.05 6.20 5.10 3.50 4.10 0.45
NOTE
A A1 D E D1 E1 b e e1 L
0.50
0.60
0.70
10/13/05 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8Y7, 8-lead (6.00 x 4.90 mm Body) Ultra-Thin SOIC Array Package (UTSAP) Y7 DRAWING NO. 8Y7 REV. B
R
17
5112D-SEEPR-3/07
8U4-1 - dBGA2
A1 BALL PAD CORNER D
5.
b
E
A1
TOP VIEW
A2
A1 BALL PAD CORNER
A
2
1
SIDE VIEW
A B
e
C D
(e1)
d (d1)
BOTTOM VIEW
8 SOLDER BALLS
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE
A A1 A2 b D E
e e1
0.81 0.15 0.40 0.25
d
5. Dimension 'b' is measured at the maximum solder ball diameter.
d1
0.91 1.00 0.20 0.25 0.45 0.50 0.30 0.35 2.47 BSC 4.07 BSC 0.75 BSC 0.74 REF 0.75 BSC 0.80 REF
1/5/05
This drawing is for general information only.
TITLE
R
1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906
DRAWING NO.
REV. A
8U4-1, 8-ball, 2.47 x 4.07 mm Body, 0.75 mm pitch, Small Die Ball Grid Array Package (dBGA2)
PO8U4-1
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AT24C512B [Preliminary]
5112D-SEEPR-3/07
AT24C512B [Preliminary]
Revision History
Doc. Rev. 5112D
Date 3/2007
Comments Removed No Connect row from Pin Configuration table Removed Note from page 6 Replaced figure 4 with the correct figure Removed MSB and LSB from Figures 8-11 Added missing Figure 12 Modify 8-ball dBGA2 drawing on page 1 Add lines between Ordering Information table on page 11 Remove AT24C512BU4-UU25-T offering from ordering information Add 2.5V offering Delete 2.7V offering Add 8Y7 package drawing Add dBGA2 package Add AT24C512BU4-UU-T to page 1 and ordering information Add 2.7V offering and 2.7V characteristics Pg 1 Remove Preliminary Add Advance Information Add EIAJ SOIC part number offering to Pg 1 and Pg 12 Add EIAJ pkg drawing Changes to Ordering information, page 12; replaced 8Y4 package with 8Y7 (UTSAP) package drawing Page 1 - added ultra thin SAP to features and description Initial document release
5112C
1/2007
5112B
7/2006
5112A
8/2005
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5112D-SEEPR-3/07
Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Europe
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Microcontrollers
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Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
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Asia
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Literature Requests
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5112D-SEEPR-3/07


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